a4e667de10
Single-commit clean baseline after security scrub of niche-tells, project codenames, internal jargon, and contributor-email leaks. Contents: - 100 Rust crates (_primitives/_rust/) - 37 agent manifests (_manifests/) + generated specs (_generated/) - 67 user-invocable skills (skills/) - 33 hooks (hooks/) - Composition blocks (_blocks/) - Documentation (docs/, README.md) - TS adapter packages (_ts_packages/) - Assembler (_assembler/) - Roles (_roles/) - Templates (_templates/) - Forgejo CI (.forgejo/) Author: Denis Parfionovich <info@greendragon.info> License: see LICENSE.
32 lines
1.4 KiB
Markdown
32 lines
1.4 KiB
Markdown
# STACK — Embedded Rust STM32 (embassy / cortex-m)
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Rust-first by default. STM32H743 is a common reference MCU.
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**Crate skeleton:**
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```rust
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#![no_std]
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#![no_main]
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use embassy_executor::Spawner;
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use embassy_stm32::bind_interrupts;
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use defmt_rtt as _;
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use panic_probe as _;
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```
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**HAL choice:** embassy (async, preferred for new work) OR cortex-m-rt + HAL crates (if you need full sync control). Pick one per project; no mixing.
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**Memory budget (MANDATORY comment in `Cargo.toml`):**
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```toml
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# STM32H743ZI — flash 2 MiB, RAM 1 MiB. Current: flash 312 KiB / RAM 84 KiB.
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```
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Update on every commit that moves size by > 4 KiB.
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**I/O rules:**
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- DMA for any transfer > 32 bytes (UART, SPI, I2C, ADC bursts). Polling in ISRs bricks latency.
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- Interrupt priorities EXPLICIT via `NVIC`. Default `0` = highest — two handlers at priority 0 deadlock.
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- NO heap allocations in ISRs. `heapless::Vec` / `heapless::String` only, with compile-time capacity.
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**Allocator:** default is NO allocator (`#![no_std]` bare). If you add `alloc`, document why — usually avoidable with `heapless`.
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**Debug:** `defmt` + `probe-rs` for logging. NEVER `println!` (no stdout).
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**Forbidden:** `alloc` without justification; `.unwrap()` outside `#[cfg(debug_assertions)]`; interrupt handlers > 30 LOC (move logic to a task); DMA without `'static` buffers (UB with stack buffers); flashing without `probe-rs erase` when changing memory map.
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